Solid State Science and Technology, Vol. 16, No 2 (2008) 134-143

ISSN 0128-7389

Corresponding Author: 134



S. Yaakup, N. S. Shaari, W. N. W. Jaafar and M. A. Hashim

Advanced Materials Research Centre (AMREC), SIRIM Berhad,

Lot 34, Jalan Hi-Tech 2/3, Kulim Hi-Tech Park

09000 Kulim, Kedah



Advancement in integrated circuit (IC) chips packaging involves three-dimensional (3D) versus two-dimensional (2D) packaging technology. 3D packaging involves stacking of daughter die/s on to a mother die in a vertical configuration for obvious reasons. Interconnections had been done either through wire bonding or a combination of wire bonding and flip chip technology. Flip chip technology requires the formation of solder bumps on processed silicon wafers, which were diced to form a single diced die. Relatively expensive and elaborate evaporation and electroplating processes used in the formation of solder bumps leads to a development in a simpler and cheaper bumping technology. The present experimental work describes challenges and updates methods in stencil printing for the development of solder bumps on copper as an arbitrary substrate. Both, lead-containing and lead-free solder pastes were used as the bumping materials of construction. Green solder bumps were heated in an atmospheric furnace with controlled heating rate and heating time. Solder pastes characterisation used in this study were done using solder checker equipment. Solder bump characterizations include bump height and uniformity, composition, shear force magnitude using solder bond analyser and bump profiles and cross section analysis were conducted using scanning electron microscopy.



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