Solid State Science and Technology, Vol. 16, No 2 (2008) 33-41

ISSN 0128-7389 Corresponding Author: 33



W.M.S.W. Suliman1, W. Shualdi1, G. Kenny C.S.2 and A. Isnin 3

1Advanced Semiconductor Packaging (ASPAC) Research Laboratory

Universiti Kebangsaan Malaysia

43600 UKM Bangi, Selangor, Malaysia

2Failure Analysis Department, Infineon Technologies (Kulim) Sdn. Bhd.

09000 Kulim, Kedah, Malaysia

3Advanced Material Research Center (AMREC)

09000 Kulim, Kedah, Malaysia



Backside analysis has been developed as a useful tool for failure determination for quite some time. This method of analysis, used for debug and fault isolation required a limitless stretch of the imagination and creative solutions. The procedures used to gain access to the back of the target die for backside Photoemission Microscopy have created many unique and challenging solution of their own. With the speed of change, advancement and developments within the power semiconductor technology, multi layer metallization and shrink processes make traditional front or top side analysis technique more difficult and in most cases impossible. Technological advancement results in utilization of backside analysis technique to become an important tool for debug and fault isolation.


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